5. The Register File and Building an ALU
Register File
Remember this?
Well, there is some unresolved questions like what's the control, datapath, how does it know what instruction to get next, how does it know what registers to access, how does it know to add, substract, etc.?
Let's zoom in and look at the few major parts of any CPU.
With a bit less abstraction, the registers are grouped together into a register file. The ALU (arithmetic and logic unit) is the main part of the datapath. The control is doing its thing, we'll see soon.
it doesn't have to be this way
CISC CPUs usually have small sets of registers, and many have special purposes or behaviors.
RISC CPUs usually have 32 mostly-interchangeable registers: MIPS, RISC, SPARC, ARMv8, RISC-V...
The register file design is constrained by many competing factors.
Advice
You will see many imperfect designs in your life.
But in problem-solving, perfection isn't always the goal. Everyone has to work within the constraints they're given.
If everyone does something the same way. There are probably problems/constraints you don't know about. DON'T WASTE YOUR TIME REINVENTING THE WHEEL. Find out why it's done that way first.
When it comes to register files, 32 registers is just a nice number.
Let's create a register.
Grrrr, just abstract it away lol.
Then put multiple regsters together to make the register file.
What does the register file need to do?
Why? well consider add t0, t1, t2. We need to read two registers and write one register.
The write enable is used when you want to write to a register.
Let's simplify to two registers, we need to choose which one to read. We use a multiplexer.
For the write port, we only want to write to one register at a time. We will need a select signal again. Use a demultiplexer to select the write enable.
Wait, do we always have to write to a register? Like beq A, 3, top or sw A, t0?
We can account for that, when a register's write enable is 0, we can hook up the data input to all registers at one. Only the register with WE = 1 will store the data.
Now let's look at our register file again, assume we have 32 registers with 32-bit sizes.
Arithmetic and Logic Unit (ALU)
What is a component that does arithmetic? A one-bit adder!
Now, what if we want to substract? Well add a mutiplexer. We will have some more control signals leading into it and several outputs.
Let's put it into a box. Below is addition.
This is subtraction.
Let's expand it into a 1-bit ALU. This ALU can perform the arithmetic operations add and subtract as well as the logic operations AND, OR, NOT. The operation is selected by the signal operation: 00-AND; 01-OR; 10-ADD; 11-SLT.
Some examples of this ALU. First addition.
Subtraction.
AND.
OR.
NAND with some boolean algebra.
And NOR.
To do a NOT, do a NAND with A=A and B=A use the same input.
This ALU can detect overflow which also allos to perform the SLT operation. Remember that the slt instruction is the basis of other conditionals. For instance, blt t0, t1, label is equivalent to slt at, t0, t1 and bne at, zero, label. slt is set if less than:
- "Set" = 1 if a < b
- "Set" = 0 if a >= b
Or can we really support overflow, use an xor gate.
What is the propagation delay? Well, assume not=2ns, mux=6ns, adder=10ns, and/or/xor=4ns. The total delay is 26ns.
Now like everything we have been doing, we can combine multiple 1-bit ALUs. We can also combine the Binvert and Carry in signals since they are used simultaneously for substractions otherwise, we don't care about the carry in.
To implement slt, remember that slt uses substraction: slt at, t0, t1, t0 < t1 => t0 - t1 < 0 then set is 1. Also notice how set is connected to ALU0's less input. We can't use the Result31 since the ouput is 0, not 1.
Let's make a 32-bit ALU.
Yikes, let's again, abstract that away.
ALUs are many times in the real world built as multiple 1-bit ALUs, which is called bit-slicing. However, we can build it much like the 1-bit model, but just tell Logisim to make the components "data size" of 32-bits.
Zooming Out
WoW, we now have a register file and an ALU, we can almost build an entire CPU.
