4. Sequential Logic

Latch

How do we store things, we use latches and yes we can do this.

To think of the S/R latch correctly, think when the loop will become "stable" (see animation below). (R)eset means make it zero and (S)et make it one. Do not make then both zero or both one since both ones will produce an illogical result and both zeros will produce an oscillation.

For table below, Q is the current value of Q and $Q_{next}$ is the new value.

Clock

Since electrons don't move instantly, there is a propagation delay with our S/R latch that needs to be addressed. The propagation delay is the time it takes for a signal to pass from the inputs to the outputs. During that delay, the outputs are invalid and after the delay, the outputs are valid.

To determine the propagation delay, you need the critical path which is the longest series of sequential operations.

This is an example of a propagation.

If there is a component after the S/R latch that needs to reach on the data of Q, then we need to synchronize. In other words, we need to wait until the Q value if updated. We could use something that periodically and predictably updates in an interval that is a little longer than the propagation delay.

Oh wait we just described a clock.

Sequential logic is based on time, and time is continuous

This clock signal goes 0, 1, 0, 1, 0, 1, ... Each period is called a clock cycle.

Now that we thought of a clock, how do we actually use it. Well, we need to augment our latch to wait for the clock before updating the value. We also need to account for the clock signal and only transmit a "1" on R or S if and only if the clock is high (or low). So, we can do this:

Or... we could simplify into a D-latch, "C" is the clock and "D" is the data to latch when the clock is high.

Circuit only changes the value when the clock signal is 1. Latches when clock is 0

When clock is low, D is don't care.

When clock is high and D is high (set operation).

When clock is high and D is low (reset operation).

Or... just abstract it away.

Generally, the "C" for clock is omited and a triangle is used instead.

This below, is a diagram of the system over time.

What if we don't want to change the value of Q. So we need to constantly recharge the value, that is "D" has to be what we want Q to be every tick, which limits the usefulness.

So add an and with (W)rite enable that is usually kept at "0" and only allow the latch when it is "1"

Or we can use a multiplexer:

Also, never do this.

Flip-Flop

Well, the clocks don't always help with the propagation delay. We sometimes need a clock cycle to compute a value and then another clock cycle to compute the next thing but the next thing needs to be computing the CURRENT thing but we would overwrite that input... so it would compute something else before it was done computing the first thing and AHHHHH!!!

So, we want to record an intent to store (latch) a value. That is to delay the latch by around a cycle. But only actually do it at an idle moment. When do we have an idle moment in the latch? When the clock is low.

If we cascade two D-Latches, and handle the clock well... We can create a register! (aka a D Flip-Flop).

We will create a component that latches a value on the clock's falling edge.

While the clock is “1” (high), D’ can be computed while Q remains unaffected. Q is being used, after all, by whatever component is after the flip-flop. While D is not immediately known and is being computed by the component before the flip-flop.

Falling clock edge: value is copied from the first latch to the second. This handles data propagation within a sequential circuit.

With this we are using the clock edges, the circuit only updates its output in the instant the clock changes. During the remaining time, other circuits can compute values.

This is a diagram of the behavior over time.

And to abstract it away into a 1-bit register.

Which is really this.

Real-World Clocking Issues

To determine clock speed, do finished-start

So this takes $5ns$ for a signal to propagate through our circuit. How fast can we clock it? Well, if the time between clocks is less than $5ns$, then we will clock the register too early (while the adder's outputs are invalid). If the time between clocks is more than $5ns$ then no big deal.

The fastest we can clock a sequential circuit is the reciprocial of the cirical path's propagation delay.

$\frac{1}{5\cdot 10^{-9}s}=0.2\cdot 10^9 Hz=200MHz$

Also, the clock signal itself is not immune to propagation delay.

Circuits Using Flip-Flops

Let's say we have three 1-bit registers: A, B, C. We would like to compute C = A + B. We need three D Flip-Flops and a 1-bit adder.

Or even do A = A + B

We could also build a counter. This is a register that increments every clock tick (on the falling-edge in this case).

Wait, adding takes some time because it ripples, so how long does our clock cycle have to be? Well, no shorter than the propagation delay. Assuming latches take 2ns and adders take 4ns, it would take 20ns. The D Flip-Flops are in parallel, so they take 2ns then another 2ns to fully update. The adders are in series, so 4*4ns = 16ns. Thus, 2ns+16ns+2ns=20ns to fully wait for all output bits to stablize.

If it takes 20ns, then this bounds our clock speed. Which is $\frac{1}{20 ns}=50000000 Hz = 50 MHz$.

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